VHDL Modeling for Digital Design Synthesis [Paperback]

ISBN: 9789384007003

Edition: 1st

Author : S. Ramamurthy, V.P. Kothari

Year: 2014

Pages: 376

Size: 14 x 21.5

Publisher Name: MedTech

Rs. 0.00
Rs. 395.00

The purpose of the book "VHDL Modeling for Digital Design Synthesis" is to introduce VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that permitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the implementation technology. VHDL has data structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. This book covers the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is primarily designed for working professionals as well as for graduate or undergraduate students. Readers can use this book to get acquainted with VHDL and to learn how it can be used in modeling of digital designs.

1.     INTRODUCTION

2.     BASIC STRUCTURES IN VHDL

3.     TYPES, OPERATORS AND EXPRESSIONS

4.     SEQUENTIAL STATEMENTS

5.     CONCURRENT STATEMENTS

6.     SUBPROGRAMS AND PACKAGES

7.     MODELING AT THE STRUCTURAL LEVEL

8.     MODELING AT THE RT LEVEL

9.     MODELING AT THE FSMD LEVEL

10.   MODELING AT THE ALGORITHMIC LEVEL

11.   MEMORIES

12.   VHDL SYNTHESIS

13.   WRITING EFFICIENT VHDL DESCRIPTIONS

14.   PRACTICING DESIGNS

REFERENCES

A    RESERVED WORKS

B    STANDARD LIBRARY PACKAGES

INDEX

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